As clock speeds in low power dynamic random access memory (LPDRAM) devices increases, duty cycle distortion becomes common on the falling edge of the clock signals. In double data rate (DDR) devices, which provide output data on both the rising edge and the falling edge of the clock signal, the duty cycle distortion can negatively affect performance. However, correcting the duty cycle distortion often involves complex clock generators that result in significant power consumption. Accordingly, there is a need for a circuit can provide the requisite clock signals while reducing or minimizing clock path power consumption without sacrificing performance.